1. Field of the Invention
The present invention is related to a data-processing module, and more particularly, to a data-processing module capable of being connected in series to form a cascading data-transmitting system.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional cascading data-transmitting system 100. The cascading data-transmitting system 100 includes a main controller 110, and data-processing modules DPM1˜DPMN. The main controller 110 is utilized for generating a clock signal SCLK, a command serial signal SCMD, a command-latching signal SLC, and a data-latching signal SLD. The data-processing modules DPM1˜DPMN is utilized for handling the data transmitted by the main controller 110 through the command serial signal SCMD. The data-processing modules DPM1˜DPMN are coupled in series. Each of the data-processing modules DPM1˜DPMN includes a first-in-first-out (FIFO) buffering circuit, a command register, and a data register.
Please refer to FIG. 2. The structure and the operation principle of the data-processing module DPM1 is illustrated for example. The data-processing module DPM1 includes an FIFO buffering circuit FBC1, a command register CR1, and a data register DR1. The FIFO buffering circuit FBC1 is utilized for transmitting and temporarily storing the command serial signal SCMD according to the clock signal SCLK. The FIFO buffering circuit FBC1 includes K buffering units TUK˜TUK. The buffering units TU1˜TUK are coupled in series. Each buffering unit is utilized for temporarily storing one bit of the data transmitted by the command serial signal SCMD. When a buffering unit receives the clock signal SCLK, the buffering unit transmits the bit presently stored in the buffering unit and the clock signal SCLK to the next-stage buffering unit. For example, the previous stage of the buffering unit TUA is the buffering unit TU(A+1), and the next stage of the buffering unit TUA is the buffering unit TU(A−1). It is assumed that at the beginning, the bit of the command serial signal SCMD stored in the buffering unit TU(A+1) represents logic “0”; the bit of the command serial signal SCMD stored in the buffering unit TUA represents logic “1”; and the bit of the command serial signal SCMD stored in the buffering unit TU(A−1) represents logic “0”. When the buffering units TU(A+1), TUA, and TU(A−1) receive the clock signal SCLK, the buffering unit TUA outputs the bit, which is stored in the buffering unit TUA and represents logic “1”, to the next-stage buffering unit TU(A−1), and simultaneously receives and stores the bit, which is outputted by the previous-stage buffering unit TU(A+1) and represents logic “0”. Meanwhile, the bit stored in the buffering unit TUA represents logic “0”, and the bit stored in the buffering unit TU(A−1) represents logic “1”. The command register CR1 is utilized for latching command according to the command-latching signal SLC transmitted by the main controller 110. More particularly, when the command register CR1 receives the command-latching signal SLC transmitted by the main controller 110, the command register CR1 stores the data transmitted by the command serial signal SCMD temporarily stored in the FIFO buffering circuit FBC1 (that is, the command register CR1 stores the data temporarily stored in the buffering units TU1˜TUK). The data register DR1 is utilized for latching data according to the data-latching signal SLD transmitted by the main controller 110. More particularly, when the data register DR1 receives the data-latching signal SLD transmitted by the main controller 110, the data register DR1 stores the data transmitted by the command serial signal SCMD temporarily stored in the FIFO buffering circuit FBC1 (that is, the data register DR1 stores the data temporarily stored in the buffering units TU1˜TUK).
In general, the data-processing module is realized by a chip. However, according to the above-mentioned description, the data-processing module requires an additional pin as a latching pin for receiving the latching signals (the command-latching signal and the data-latching signal) transmitted by the main controller, so as to control the command register to latch command or control the data register to latch data. Hence, the cost of the data-processing module increases. Since in the cascading data-transmitting system, the number of the data-processing modules is quite large, the additional pin required by the data-processing module vastly increases the cost of the cascading data-transmitting system, causing a great inconvenience.